1. Field of the Invention
The present invention relates to a circuit of a semiconductor device, and more particularly, to a data out circuit of a DRAM. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a data out speed and providing a reliable data out circuit of a DRAM.
2. Discussion of the Related Art
An EDO (Extended Data Out) mode is generally used for an efficient and stable data out even in a short cycle for a high speed access to DRAM devices. The EDO mode employs a concept of a data latch for a faster cycling in a fast page mode, so that the first pipeline latch in the circuit is used to keep data out even when a CASB(Column Address Strobe Bar) is high. Accordingly, the data out circuit keeps outputting the present data until the next data out occurs following the address change, thereby making a stable data out even within a short cycle.
A background art data out circuit of a DRAM will be described with reference to FIG. 1 illustrating a block diagram illustrating a data out circuit of a DRAM according to a background art.
In the background art data out circuit of a DRAM of FIG. 1, a column address transition signal is not transmitted to a DOE(Data Output Enable) signal which controls a data out by opening a data out buffer in read operation. The data circuit includes a normal operation determining part 11, a write/read determining part 12, a delay part 13 and a DOE generating part 14.
The normal operation determining part 11 receives a RASB(Row Address Strobe Bar) and a CASB and determines whether it is a normal operation or an abnormal operation by transmitting the CASB to low and receiving the above column address. The normal operation is to read or write a data for a desired address whereas the abnormal operation is to determine a CBR(CAS before RAS), which is the CASB transits to low before the RASB transits to low.
The write/read determining part 12 receives a WEB(Write Enable Bar) and determines whether it is a read operation when the WEB is low, and it is a read operation when the WEB is high.
The operation of the aforementioned data out circuit of a DRAM will be describe with reference to FIG. 2.
As shown in FIG. 2, there are different pulses of RASB, CASB, address, EQMB (Equalizer Middle Bar), OEC (Out Enable Control), DOE (Data Output Enable),and an output data. If the normal operation determining part 11 determines it is a normal operation, the write/read determining part 12 determines it is a read when the RASB is transited to low in an EDO mode, a row address is received. Upon receiving the row address, a row system circuit is operated. If the CASB is transited to low, a column address is received and the DOE generating part 14 generates a DOE signal. Thus, a data out is ready to be executed according to outputs from the normal operation determining part 11, the write/read determining part 12 and the delay part 13. In other words, a data out is executed after satisfying a tCAA (Column Address Access Time).
When a tCAS (Column Address Setup Time)--a setup time between the column address and CASB--is -5 nS.about.+5 nS, the OEC of the delay part 13 is always high by receiving the high HPH. When the CASB becomes low, a data is outputted immediately since there is no control for the data out buffer. Consequently, an invalid data is outputted through the data out buffer in accordance with the CASB before outputting a valid data at an address designated presently. In other words, the valid data is outputted after the invalid data is outputted during the first cycle.
The background art data out circuits of a DRAM has the following problems.
In the data out circuit of a DRAM according to the background art, since a column address transition signal is not provided to the DOE, there is a delay in speed and an instability in system operation. This problem is caused by an invalid data provided during the first cycle coming from the outputted data when the CASB is transited to low since there is no data out buffer control.
Further, the background art data out circuit of a DRAM attempts to solve the problem caused by DOE not having a column address transition signal. However, the background art data out circuit data causes an invalid signal because a latch part is inoperative as the EQMB is high at the tASC of 7.about.9 nS, so that the tAA speed varies with the tASC. Accordingly, a system operation malfunction and a frequent transition of the DOE occurs in the background art data out circuit of the DRAM, thereby reducing a data out speed.